Novel Architecture of High Speed Parallel MAC using Carry Select Adder

In this paper, new hardware architecture of multiplier and accumulator (MAC) for high speed arithmetic was designed. The performance was improved by merging multiplication with accumulation and organize a hybrid type carry save adder (CSA). The proposed CSA tree uses 1's complement based radix-4 and radix-8 modified booth algorithm(MBA). The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to reduce the number of the input bits of the final adder. This MAC add the intermediate results in the form of sum and carry bits instead of the final adder output, which made it possible to optimize the pipeline system to improve the performance. The final addition was carried out by high speed carry select adder (CSLA) with binary to excess convertor using CLA. Based on the theoretical and experimental estimation, we analyzed the results in terms of delay. The design is implemented using VHDL language and simulated using Xilinx ISE10. 1 Simulator.